1. Field of the Invention
The invention relates to an electrostatic discharge (ESD) protection device.
2. Description of the Prior Art
With the continued miniaturization of integrated circuit (IC) devices, the current trend in the sub-quarter-micron complementary metal-oxide semiconductor (CMOS) industry is to produce integrated circuits having shallower junction depths, thinner gate oxides, lightly-doped drain (LDD) structures, shallow trench isolation (STI) structures, and self-aligned silicide (salicide) processes. Nevertheless, all of these processes cause the related CMOS IC products to become more susceptible to electrostatic discharge (ESD) damage. Therefore, ESD protection circuits are built onto the chip to protect the devices and circuits of the IC against ESD damage. It is generally desired that the ESD robustness for commercial IC products be higher than 2 kV in human-body-model (HBM) ESD stress, and in order to sustain ESD overstress, devices with large dimensions need to be designed into the on-chip ESD protection circuit, and require a large total layout area on the silicon substrate.
Typically, the NMOS of an I/O ESD protection circuit has a total channel width of greater than 300 μm. With such large device dimensions, the NMOS is often realized with multiple fingers in the layout. However, under ESD stress, the multiple fingers of ESD protection NMOS do not uniformly turn on to bypass the ESD current. Only a portion of the fingers of the NMOS may be turned on, and consequently lead to damage from the ESD pulse. In this case, although the ESD protection NMOS has a very large device dimension, the ESD protection level is low.
In order to improve the turn-on uniformity among the multiple fingers, a gate-driven design has been commonly used to increase the protection level of the ESD protection device within large scale NMOS devices. However, it has been found that the ESD protection level of the gate-driven NMOS decreases dramatically when the gate voltage is somewhat increased. As it turns out, the gate-driven design pulls ESD current flowing through the channel surface of the NMOS. The NMOS is thus more easily burnt-out by the ESD energy.
Please refer to FIG. 1. FIG. 1 is a schematic circuit diagram of a conventional ESD protection design by utilizing a gate-driven technique. Since all ESD protection designs using the gate-driven technique have the same basic idea, they may be generally illustrated as disclosed in FIG. 1. As shown in FIG. 1, the ESD protection circuit design 10 includes an ESD protection NMOS 12. The NMOS 12 includes a source 13, a drain 14 and a gate 16. The drain 14 of the NMOS 12 is electrically connected to a pad 18 and the gate 16 is biased by a gate-biasing circuit 20. The gate-biasing circuit 20 is typically designed with a coupled capacitor (not shown) electrically connected from the pad 18 to the gate and a resistor (not shown) electrically connected from the gate 16 to a VSS power terminal. Additionally, an internal circuit 22 is electrically connected to the pad 18 through a conductor 23.
When a positive ESD voltage zaps the pad 18, a sharp-rising ESD voltage pulse is coupled to the gate 16 of the ESD protection NMOS 12. The ESD protection NMOS 12 is thus turned on to discharge the ESD current from the pad 18 to the VSS power terminal. This is the so-called gate-coupled design or gate-driven design. The gate bias improves the turn-on uniformity of the multiple fingers of the ESD protection NMOS, but an excessive gate bias also causes the ESD current to flow through the inversion layer of the surface channel of the ESD protection NMOS 12, which can burn out the channel of the NMOS 12.
Please refer to FIG. 2. FIG. 2 is a schematic diagram of an ESD current path flowing through a gate-driven NMOS device. As shown in FIG. 2, an ESD protection NMOS device 30 includes a P substrate 31, a P-well 32 in the P substrate 31, and an NMOS transistor 34 in the P-well 32. The NMOS transistor 34 includes a source 35, a drain 36 and a doped polysilicon gate 37, and two lightly doped drains (LDD) 38 adjacent to the source 35 and drain 36 respectively. The source 35 region is electrically connected to a VSS power terminal, the drain 36 region is electrically connected to a pad 40, and the gate 37 region is electrically connected to a gate-biasing circuit 42. In FIG. 2, ESD damage is often located at the surface channel close to the LDD 38 edge of the drain 36.
The gate-biasing circuit 42 generates a high voltage (VG) to bias the gate 37 of the NMOS transistor 34 during positive ESD zapping events. The generated VG gate voltage turns on the surface channel of the NMOS. Unfortunately, the surface channel of the NMOS 34 having a structure with a much shallower junction depth and smaller volume is more susceptible to ESD damage. As a result, the overheating caused by the damage may also damage the NMOS 34 itself. The ESD damage is often located at the surface channel close to the LDD 38 corner of the drain 36. In general, a large ESD current (typically 1.33 Amp, for a 2 kV HMB ESD event) flowing through the very shallow surface channel of the NMOS transistor 34 often burns out the NMOS transistor 34 even if the NMOS 34 has large device dimensions.
Please refer to FIG. 3. FIG. 3 is a perspective diagram showing the means of forming a diffusion region below the well of a conventional ESD protection device. As shown in FIG. 3, in order to reduce the burnout of the surface channel of the NMOS 34, a P+ diffusion region 33 is often formed below the drain 36 of the conventional ESD protection device 30 to lower the breakdown voltage of the PN junction formed between the drain 36 and the P-well 32. Since the P+ diffusion region 33 is formed below the drain 36, processes including a deep well fabrication process, a salicide block (SAB) mask, and an ion implantation have to be performed or utilized to lower the breakdown voltage between junctions to improve the efficiency of the ESD protection device, and thereby increase the complexity of the fabrication processes and cause misalignment problems.